Electronics Cooling Toolset: Natural Convection JEDEC

Although many electronic devices benefit from cooling fans in removing excess heat, some devices rely on natural convection only. The Electronics Cooling Toolset includes a method for estimating cooling due to natural convection.

The simulation models the JEDEC standard test method for integrated circuits in natural convection [957]. The purpose of this test method is to measure the junction-to-ambient ( θ J A ) thermal resistance of a chip package in a standardized still air environment. θ J A allows a thermal performance comparison between chip packages and is calculated as:

θ J A = T J T A P H

where:

  • T J is the junction temperature of the chip package.
  • T A is the ambient temperature.
  • P H is the power dissipation of the integrated circuit.

In this tutorial, the test package is a generic BGA (ball grid array) package, depicted as follows:



The test standard arranges the chip package on a test board in the center of a closed chamber:



In this tutorial, you build the complete geometry of the test rig, the chip package, and the chamber using templated QuickParts. The analysis includes the following heat transfer modes:

  • Conduction in the solid components of the test rig, the chip package, and the chamber.
  • Diffusion, natural convection, and radiation in the enclosed air.

To conclude the analysis, you display the simulation results using the post-processing capabilities that are available in the Electronics Cooling Toolset.