Chip

The following image displays the various elements of a chip package:

To represent the geometry of a chip package, the Electronics Cooling Toolset supports the following Chip QuickParts:


Block	Cylinder

If the built-in shape templates are not suitable, you can define a Custom chip whose geometry is based on a Construction Geometry that you specify.

To represent the physics of a chip package, two thermal modeling approaches are available:

Solid model: represents the chip package as a single solid part of a specified material. A total heat source models the excess heat of the package.
Compact thermal model (CTM) ([144], [145]): a simplified component model that mimics the performance of the chip package within the system-level analysis. It represents the critical heat flow paths within the package using a thermal resistor network. Each network node corresponds to a surface of the package or a region within the package and is associated with a single temperature.

A CTM of a chip package is more accurate than a solid model. As a CTM does not require a volume mesh within the package, it is also computationally less expensive. On the other hand, the resistor network of a CTM requires that you have access to detailed information about the heat flow paths within the package. The following types of resistor networks are available:


Two Resistor		Star Network	Delphi Network

The various network types differ in the number of nodes and the connections between them. Each resistor network owns the following three nodes:

Junction node—that represents the integrated circuit.
Case node—that describes the top surface of the package.
Board node—that is considered as the contact between the package and the PCB.

A Star Network adds additional nodes to the side surfaces. A Delphi Network splits the top surface and the contacting area between the package and the PCB in an inner and an outer area, respectively, and represents them by separate nodes.

Two resistor and Delphi networks are suitable for packages where the heat transfer through the sides can be ignored. For example, within a typical BGA (ball grid array) package most of the heat flows through the solderballs to the PCB at the bottom and/or to the heatsink on top. A two resistor network assumes uniform temperatures on the top and bottom surfaces, whereas a Delphi network relaxes this assumption by allowing different temperature in the inner and outer areas of the surfaces.

Star networks are suitable for packages where the heat transfer through the sides can not be neglected. For example, within a leaded package the heat flow path through the sides significantly affects the package temperature. The available star network assumes a uniform temperature across the side surfaces.

Within the Electronics Cooling Module, each network node—apart from the junction node—corresponds to a QuickPart Surface of constant and uniform temperature. Surfaces without a network node are modeled as adiabatic. For more information, see Resistor Networks Formulation.

Chip—Properties

The following properties are common to all types of chip packages:


Name	Specifies the name of the chip under which it is stored in the tree.
Geometry	Local Origin Specifies the location of the chip's local coordinate system. See X_or, Y_or, Z_or in the Graphics window. It is used for placing the chip in the simulation domain. The following options are available: Bottom Center: Center of the Zmin face. Bottom Corner 1 (block chips only): Xmin/Ymin/Zmin corner of the block. Bottom Corner 2 (block chips only): Xmin/Ymax/Zmin corner of the block. Center: Center of the geometry. Custom: This value appears when you set the local origin interactively within the Graphics window, see Placing Object Interactively.
Placement	See Placement properties.
Physics	Material Specification Controls the thermal modeling approach for the chip package. The following options are available: Default Material Specification: Models the chip package as a solid part. You select the Material of the solid part from the Solid Sim Materials that you define in the Setup panel. The Heat Source value specifies the total heat generated by the package. This option is available for templated and customized chip geometries. Two Resistor, Star Network, or Delphi Network: Models a chip package using the CTM approach. These options are available for templated chip geometries only. The Star Network and the Delphi Network options are further restricted to block geometries. For chips imported from an IDF file, note that the IDF standards 2.0 and 3.0 only support 2-resistor network topologies.

The following properties characterize the different geometrical types:

Block—Specific Properties


Geometry	X, Y, Z Specifies the size of the block in x-, y, and z-direction, in the chip's local coordinate system. See X_or, Y_or, Z_or in the Graphics window.

Cylinder—Specific Properties


Geometry	Radius Specifies the radius of the cylinder. Height Specifies the extent of the cylinder from bottom to top.

Custom—Specific Properties


Geometry	Selected Construction Geometry Specifies the Construction Geometry that describes the geometry of the chip. If you select multiple Construction Geometries when creating a Custom chip, the Electronics Cooling Toolset automatically creates multiple chips that own the same physics.

The following tables display the properties of the available resistor networks:

Note

Request the required input values from the package supplier or derive them from JEDEC-standard thermal tests. Alternatively, you can extract the values from a detailed thermal model of the package using a statistical optimization process that minimizes errors in junction and surface temperatures for a variety of environmental conditions.

Two Resistor



$θ j c$ , $θ j b$ Specify the thermal resistance between the respective network nodes, see diagram above. Heat Source The total heating power of the integrated circuit that is applied at the junction node J.

Star Network



$θ j c$ , $θ j b$ , $θ j s$ Specify the thermal resistance between the respective network nodes, see diagram above. Heat Source Specifies total heating power of the integrated circuit that is applied at the junction node J.

Delphi Network



% Top inner area, % Bottom inner area Specify the top inner and bottom inner area ratios, respectively. $θ j T i$ , $θ j T o$ , $θ j B i$ , $θ j B o$ , S1, S2, S3 Specify the thermal resistance between the respective network nodes, see diagram above. Heat Source Specifies total heating power of the integrated circuit that is applied at the junction node J.